The present invention generally relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device comprising a recess transistor and a method for manufacturing the same.
Due to the high integration levels required by semiconductor devices, a process margin for forming an active region and a device isolation structure has been decreased. As a critical dimension (“CD”) of a gate becomes smaller, a channel length is reduced, thereby resulting in a short channel effect (“SCE”), which degrades the electrical properties of the semiconductor devices. The short channel effect degrades a refresh property of the gate. In order to prevent the short channel effect, a recess gate may be used. The recess gate is obtained by etching a portion of a semiconductor substrate, so as to enlarge a contact area between the active region and the gate, thereby increasing a gate channel length.
FIG. 1 is a top view illustrating a conventional semiconductor device. An active region 20 and a device isolation structure 30 are formed on a semiconductor substrate 10. A recess region 60 is formed by etching a portion of active region 20 that overlaps a gate region 70a. A gate 70 is formed in recess region 60. Because gate 70 is formed in recess region 60, gate 70 is often referred to as a recess gate.
FIG. 2 is a cross-sectional view illustrating the semiconductor device taken along line A-A′ of FIG. 1. As shown in FIG. 2, gate 70 is formed in recess region 60. Because gate 70 is formed in recess region 60 obtained by etching active region 20, a channel length of gate 70 is increased.
However, as a semiconductor device becomes smaller, there is a limit in using recess region 60 to increase the channel length of gate 70. A process margin for forming a landing plug contact region by recess region 60 is reduced. As a result, in order to secure the channel length to a given value, it is required to decrease a width of recess region 60 and to increase a depth of recess region 60, so as to comply with the reduced process margin.